The evolution of electronic packaging can be categorized into three generations. The first generation of the electronic packages is called the discrete board package, which used discrete passive components that took more than 80% of the board area to fulfill the supporting function to the integrated circuit (IC). The second generation of electronic packages used technologies such as chip scale packaging (CSP) and multi-chip-module (MCM) to increase the IC efficiency to 30-40%. The third generation of electronic packages, system on a package (SOP), proposed by the Packaging Research Center of Georgia Tech, will be based on a single-level integrated module (SLIM) technology. SLIM employs a low-cost large-area organic substrate on which consists a multiple-level structure capable of providing power, ground, and controlled impedance interconnection functions, together with a full range of integral passives.
Incorporation of passives, RF, and optical component functionalities on-chip as in the System-on-Chip (SOC) approach is an ideal way of achieving very high packaging efficiency. However, there are a number of barriers in the implementation of such an approach. First, next generation broadband communications require a combination of technologies like silicon (Si) and gallium arsenide (GaAs), and incorporating them on a single chip is very difficult. Second, added functionality on to the chip increases the number of fabrication steps, thus lowering the yield and greatly increasing the cost of SOC. Third, the product design cycle of SOC can be extended as each product will be highly application specific and require a complete redesign to incorporate new functions or modify existing ones.
The alternate SOP approach to miniaturization has a potential to achieve a high level of integration with lower projected costs, similar performance benefits, a high degree of design flexibility, and very low projected time to market. Thus, when further integration on chip becomes cost preventive, functional elements may be integrated into the package in the SOP fashion. The SOP approach may be the best solution to meet the requirements of the next generation digital consumer, telecommunication, and automotive electronics. For example, more than 70% of the area of printed wiring boards (PWB) of a typical electronic product is occupied by passive components. Therefore, integration of passive components inside the substrate, i.e., embedded passives, is one of the key features of SOP.
The fundamental building blocks for all electronic systems are active and passive components and the interconnecting substrate. An active component is one that can control current or voltage. Active components such as transistors and ICs are used for amplification, rectification, or to switch or change energy from one form to another. A passive component does not generate voltage or current. Components such as capacitors, resistors, and inductors are passive components. Their electrical characteristics are needed to form a complete circuit with voltage and current sources and active components in electronic equipment.
Passive components can be implemented in any of the following ways: (1) Discrete: a single purpose passive component is enclosed in a single case that must be mounted to an interconnecting substrate (or board); (2) Integrated: multiple passive components are integrated within a single package or module; (3) Integral: functional passive components are formed on a layer within the interconnecting substrate; and (4) On-Chip: functional passive components are a part of the active silicon IC die itself.
Currently, the majority of passive components are employed in electronic systems as discrete components. Small discrete components dominate the PWB design in a typical hand held electronic product, such as a camcorder, which today may consist of only about 20 ICs compared to 300-400 passive components. Thus, the influence that passive components have on system cost, size, and reliability is substantial. In order to meet the goals of next generation electronic packaging (e.g., smaller, lighter, faster, cheaper, and more reliable products), alternatives to discrete passive components are necessary. Integral passive (IP) components are a developing technology that provides such an alternative.
Integral passive components offer many advantages over discrete components. Discrete mounting requires large board area and can introduce additional parasitic into the system, which may limit system performance. With integral passive components, the size of the board can be reduced, especially if chips can be placed above the embedded passive component. Also, embedding these components leaves free board space for mounting components that cannot be made integral. The parasitic associated with passive components are reduced because solder joints may be eliminated and shorter connections between passive components and other IC chips are possible; hence, improved electrical performance.
In the area of high performance products, discrete passive components used for functions such as bus decoupling, line termination, and initialization are speed limiting factors because of their size, configuration, and distance from the active circuit they serve. Capacitors and resistors integral to the PWB have the potential for removing speed and/or time barriers, because they can be placed much closer to the active circuit. Integral passive components can also provide reduced assembly costs, improved packaging efficiency, mass production by batch fabrication, small size, and light weight.
Discrete capacitors are used more than any other type of passive component, thereby making them integral would be advantageous. At present, there is no material suitable for replacing individual high value (>10 nF/cm2) capacitors. Due to higher frequency applications, capacitance density requirements will increase over time. It has been suggested that, by the year 2004, technology may require capacitance density values of about 100 nF/cm2 and dielectric constant values of 200. Consequently, material development is helpful to achieving integral capacitors that can accommodate future technology requirements.
Traditionally, material development efforts have focused on polymer-ceramic composite materials for embedded capacitor applications. However, there are some disadvantages using polymer-ceramic composite materials in the SOP substrate. First, polymer-ceramic composite materials having high ceramic loading have very poor adhesion. For example, the polymer-ceramic composite with dielectric constant equal to 150 has ceramic loading density as high as 85% by volume, which is about 98% by weight. At such high ceramic concentrations, the polymer-ceramic composite material has minimal adhesion. Although the adhesion of the polymer-ceramic composite increases when ceramic loading is reduced, the dielectric constant also decreases, which makes it very difficult to accommodate future technology requirements.
Thus, a heretofore unaddressed need exists in the industry to address at least the aforementioned deficiencies and/or inadequacies.